1. Field of the Invention
The present invention relates to picture processing systems and more particularly to a system for decoding pictures encoded in accordance with an MPEG standard.
2. Discussion of the Related Art
FIG. 1 represents the main elements of an MPEG decoder 8. All MPEG decoders, especially for the MPEG-2 standard, generally include a variable length decoder (VLD) 10, a run-level decoder (RLD) 11, an inverse quantizer circuit (Q.sup.-1) 12, an inverse discrete cosine transform circuit (DCT.sup.-1) 13, a half-pixel filter 14, and a memory 15. The encoded data are provided to the decoder via a bus CDin and the decoded data are output via a bus VIDout. Between the input and the output, the data pass through processing circuits 10-13 in the order indicated above, which is illustrated by arrows in dashed lines. The decoder output is provided by an adder that sums the outputs of filter 14 and of the cosine transform circuit 13. The filter 14 needs a portion of a previously decoded picture stored in memory 15.
FIG. 2A illustrates a decoding step of a portion of a currently reconstructed picture IM1. Picture decoding is carried out one macro-block at a time. A macro-block generally corresponds to one 16.times.16-pixel picture block.
FIG. 2B illustrates an exemplary format, noted 4:2:0, of a macro-block MB. The macro-block MB includes a luminance block formed by four 8.times.8-pixel blocks Y1-Y4 and by one chrominance block formed by two 8.times.8-pixel blocks U and V. An alternative format is the 4:2:2 format where the chrominance block includes two 8.times.16-pixel blocks.
In the current picture IM1 of FIG. 2A, a current macro-block MBc is being decoded, the macro-blocks that were previously decoded being represented by hatched lines. Generally, macro-block MBc is reconstructed by using a predictor macro-block MBp fetched in a previously decoded picture IM0. To find the predictor macro-block MBp, the data that serve to decode macro-block MBc provide a movement compensation vector V that defines the position of the predictor macro-block MBp with respect to the position P of macro-block MBc in the picture.
The predictor macro-block MBp is fetched in the memory 15 that stores the previously decoded picture IM0, and is provided to filter 14 while the cosine transform circuit 13 processes data corresponding to the macroblock MBc.
The decoding described above is a so-called "predicted" decoding. The decoded macro-block is also referred to as being of predicted type. In accordance with MPEG standards, there are three main types of decoding, referred to as "intra", "predicted", and "bidirectional".
An intra macro-block directly corresponds to a picture block, that is, the intra macro-block is not combined with a predictor macro-block when it is output from the cosine transform circuit 13.
A predictor macro-block, as described above, is combined with one macro-block of a previously decoded picture, and that comes, in the display order, before the currently reconstructed picture.
A bidirectional macro-block is combined with two predictor macro-blocks of two previously decoded pictures, respectively. These two pictures are respectively former (forward) and subsequent (backward) pictures, in the display order, with respect to the currently reconstructed picture. Thus, encoded pictures arrive in an order different from the display order.
In addition, each predicted or bidirectional macroblock is of a progressive or an interlaced type. When the macro-block is progressive, the DCT.sup.-1 circuit provides the lines of the macro-block in successive order. When the macro-block is interlaced, the DCT.sup.-1 circuit first provides the even lines of the macro-block, then the odd lines. In addition, the predictor macro-block that serves to decode a predicted or bidirectional macro-block is also of the progressive or interlaced-type. When the predictor macro-block is of the interlaced-type, it is partitioned into two half-macro-blocks; one half macro-block corresponds to even lines, and the other half macro-block corresponds to odd lines, each half macro-block being fetched at different positions in a same previously decoded picture.
A picture is also of the intra, predicted or bidirectional type. An intra picture contains only intra macroblocks; a predicted picture contains intra or predicted macro-blocks; and a bidirectional picture contains intra, predicted or bidirectional macro-blocks.
To provide the various decoding parameters to the various circuits of the decoder, especially vectors V and the macro-block types, the flow of encoded data includes headers. There are several types of headers:
a picture sequence header that includes in particular two quantizer tables to provide to the inverse quantizer circuit 12, one serving for the intra macro-blocks of the sequence, and the second serving for the predicted or bidirectional macro-blocks; PA1 a group of picture header, that does not include useful data for decoding; PA1 a picture header that includes the type (predicted, intra, bidirectional) of the picture and information on the use of the movement compensation vectors; PA1 a picture slice header including error correction information; and PA1 a macro-block header including the macro-block's type, a quantizer scale to be provided to the inverse quantizer circuit 12, and the components of the movement compensation vectors. Up to four vectors are provided when processing an interlaced bidirectional macro-block.
In addition, the high hierarchy headers (picture, group, sequence) can include private data serving, for example, for on-screen display. Some private data can also be used by components external to the decoder.
The various processing circuits of an MPEG decoder are frequently arranged in a pipeline architecture which can process high data flow rates but which is very complex and inflexible, that is, which is difficult to adapt to modifications of the standards and which is inadequate to exploit on-screen display and private data.
The simplest and most inexpensive solution is to couple the various processing circuits to the memory through a common bus that is controlled by a multi-task processor.
Patent application EP-A-0,503,956 (C-Cube) describes such a system including a processor that controls transfers of data on the bus and three coprocessors that execute the processing steps corresponding to circuits 10-14. Each type of transfer to be achieved via the bus corresponds to a task carried out by the processor. All tasks are concurrent and are executed at processor interrupts generated by the coprocessors. The coprocessors exchange the data to be processed and receive the instructions provided by the processor via the bus.
This system is simple, but it is incapable of handling the high data flow rates needed.